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YD-EEA

VHDL, Vivado & Basys 3

This handbook is designed to take you from your first VHDL entity to a verified, timed, and programmed design on the Digilent Basys 3. It is both a learning course and a library you can search while working.

The central habit

Do not use the FPGA as your first debugger. Describe the circuit, simulate it with a self-checking testbench, synthesize it, inspect the timing reports, and only then program the board.

What this library teaches

  • :material-code-braces: VHDL syntax

    Entities, architectures, signals, processes, types, generics, packages, state machines, and VHDL-2008.

  • :material-chip: RTL design methods

    Combinational logic, registers, clock enables, reset strategy, hierarchy, reusable components, and safe CDC.

  • :material-test-tube: Automated verification

    Assertions, reference models, exhaustive loops, file-driven vectors, scoreboards, watchdogs, and repeatable XSim scripts.

  • :material-memory: Vivado and Basys 3

    Projects, sources, constraints, synthesis, implementation, bitstreams, programming, utilization, DRC, and timing.

Your installed setup

This edition is tailored to:

Item Local setup
FPGA board Digilent Basys 3, Artix-7
FPGA part xc7a35tcpg236-1
Main clock 100 MHz oscillator, package pin W5
Design suite AMD Vivado 2026.1
Vivado location D:\FPGA\2026.1\Vivado
HDL standard VHDL-2008 where supported
Simulator Vivado Simulator: xvhdl, xelab, xsim
Documentation MkDocs Material, local port 8001

How to use the library

If you are learning, follow the learning path in order. If you are designing, jump directly to:

The hardware-description mindset

VHDL source is not a list of CPU instructions. It describes hardware that exists simultaneously:

y <= (a and b) or enable;
z <= a xor b;

Both assignments continuously drive hardware at the same time. A process is also hardware; statements inside it are evaluated sequentially during simulation, but the synthesized gates and registers operate concurrently.

Three questions prevent many beginner errors:

  1. What hardware should exist? A gate, mux, register, counter, memory, or state machine?
  2. When may state change? Normally only on a selected clock edge.
  3. How will I prove it works? Write expected behavior into the testbench before using the board.
  1. Write a short interface and behavior specification.
  2. Draw the datapath and identify all stored state.
  3. Implement the smallest complete RTL block.
  4. Compile early to catch type and syntax errors.
  5. Write a self-checking testbench with normal, boundary, and invalid cases.
  6. Run the test suite from a clean command line.
  7. Add XDC pin and timing constraints.
  8. Synthesize; inspect warnings, inferred hardware, and utilization.
  9. Implement; require timing to pass.
  10. Program the Basys 3 and perform a short hardware sanity test.

Symbols used in this site

Tip

A recommended working habit or design pattern.

Warning

Legal VHDL that is risky, ambiguous, or often synthesized into unintended hardware.

Danger

A pattern likely to cause unreliable hardware, such as unsynchronized asynchronous inputs.

Example

A reusable template. Adapt widths, names, reset polarity, and timing to the project rather than copying blindly.