Vivado, Basys 3, and your first project

Basys 3 essentials

The Digilent Basys 3 is built around an AMD/Xilinx Artix-7 FPGA.

Property	Value used in this guide
FPGA part	xc7a35tcpg236-1
System oscillator	100 MHz
Clock package pin	W5
Clock period	10 ns
On-board programming	USB-JTAG
Common peripherals	16 switches, 16 LEDs, 5 buttons, four-digit seven-segment display

The master constraint file is revision-aware. Use the official Digilent Basys 3 master XDC and confirm the board revision.

What each Vivado step does

Step	Question answered
Create/open project	Which sources, part, language, and constraints belong together?
Elaborated design	What hierarchy and RTL hardware does the source describe?
Behavioral simulation	Does the logic satisfy its functional specification?
Synthesis	What FPGA primitives can implement it?
Implementation	Where will primitives be placed and how will connections be routed?
Static timing analysis	Can every constrained path meet its required time?
Bitstream generation	Can the implemented configuration be encoded for the device?
Hardware programming	Can that bitstream be loaded through JTAG?

Simulation success does not prove synthesis success. Synthesis success does not prove timing success.

Create a VHDL project

1. Start Vivado 2026.1.
2. Choose Create Project.
3. Select RTL Project.
4. Add or create VHDL design sources.
5. Set the target language to VHDL.
6. Select part xc7a35tcpg236-1.
7. Add the Basys 3 XDC as a constraints source.
8. Create a VHDL simulation source for the testbench.
9. In the Sources pane, verify the intended top entity for both Design Sources and Simulation Sources.

If the Basys 3 appears under Boards, selecting it is convenient. Selecting the FPGA part directly remains valid and makes the real hardware target explicit.

Set VHDL-2008

The examples in this library use VHDL-2008 features. In Vivado:

1. Select the relevant VHDL files in Sources.
2. Open Source File Properties.
3. Set File Type to VHDL 2008.

Command-line compilation uses:

xvhdl -2008 source.vhd

First design: switch to LED

Design source:

library ieee;
use ieee.std_logic_1164.all;

entity switch_led is
  port (
    switch_i : in  std_logic;
    led_o    : out std_logic
  );
end entity;

architecture rtl of switch_led is
begin
  led_o <= switch_i;
end architecture;

Minimal XDC using switch 0 and LED 0:

set_property PACKAGE_PIN V17 [get_ports switch_i]
set_property IOSTANDARD LVCMOS33 [get_ports switch_i]

set_property PACKAGE_PIN U16 [get_ports led_o]
set_property IOSTANDARD LVCMOS33 [get_ports led_o]

The XDC port names must match the VHDL top-level port names exactly.

First self-checking simulation

library ieee;
use ieee.std_logic_1164.all;
use std.env.finish;

entity tb_switch_led is
end entity;

architecture sim of tb_switch_led is
  signal switch_s : std_logic := '0';
  signal led_s    : std_logic;
begin
  dut : entity work.switch_led(rtl)
    port map (switch_i => switch_s, led_o => led_s);

  stimulus : process
  begin
    switch_s <= '0';
    wait for 1 ns;
    assert led_s = '0' severity failure;

    switch_s <= '1';
    wait for 1 ns;
    assert led_s = '1' severity failure;

    report "PASS: switch_led";
    finish;
  end process;
end architecture;

This tiny test already establishes the correct habit: the expected output is executable, not manually inspected.

Program the board

After synthesis, implementation, and bitstream generation:

1. Connect the Basys 3 USB-JTAG port.
2. Turn the board on.
3. Open Hardware Manager.
4. Choose Open Target → Auto Connect.
5. Select the detected Artix-7 device.
6. Choose Program Device and select the generated .bit.

A JTAG-loaded bitstream is normally volatile: turning power off removes the configuration. Programming the on-board nonvolatile memory is a separate flow.

Recommended project directories

project/
├── src/          # Synthesizable entities and packages
├── tb/           # Testbench source and vector files
├── constraints/  # XDC files
├── sim/          # Scripts; generated outputs ignored
├── docs/         # Requirements, diagrams, notes
└── vivado/       # Project files if you choose a project-based flow

Keep source files outside opaque generated directories. This makes backup, Git, simulation scripts, and project recreation easier.

First-project checklist

• Correct part: xc7a35tcpg236-1.
• VHDL-2008 configured.
• Design and simulation top entities are correct.
• XDC ports match the top-level VHDL names.
• Testbench passes without manual waveform judgment.
• No unexplained synthesis warnings.
• Implementation timing is met.
• Bitstream was generated from the latest sources.