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VHDL language map

VHDL separates a circuit into an interface and one or more implementations.

library ieee;
use ieee.std_logic_1164.all;

entity inverter is
  port (
    input_i  : in  std_logic;
    output_o : out std_logic
  );
end entity inverter;

architecture rtl of inverter is
begin
  output_o <= not input_i;
end architecture rtl;

Design-unit vocabulary

Unit Purpose
Library clause Makes a compiled library name visible
Use clause Imports declarations from a package
Entity Declares generics and ports: the public interface
Architecture Implements an entity
Package Shares types, constants, functions, and procedures
Package body Implements deferred constants or subprogram bodies
Configuration Selects bindings; useful in some advanced flows but uncommon for small projects
Context Groups repeated library/use clauses in VHDL-2008

The two execution worlds

Concurrent region

Statements after begin in an architecture are concurrent. Order does not express execution order.

sum_o   <= a_i xor b_i xor cin_i;
carry_o <= (a_i and b_i) or (cin_i and (a_i xor b_i));

Sequential region

Statements inside a process, function, or procedure are sequential.

process(all)
begin
  if select_i = '1' then
    y_o <= b_i;
  else
    y_o <= a_i;
  end if;
end process;

The process itself is concurrent with every other process. Sequential syntax tells the simulator how that one process calculates its drivers when awakened.

Synthesizable versus simulation-only

Commonly synthesizable:

  • Combinational assignments and complete combinational processes.
  • Edge-triggered processes.
  • Bounded loops whose limits are known during elaboration.
  • Static generics and generate statements.
  • Arithmetic using numeric_std.

Usually testbench-only:

  • Arbitrary wait for 10 ns delays.
  • Reading and writing ordinary text files.
  • assert used as a verification oracle.
  • std.env.finish.
  • Dynamically allocating access types.

Note

Some assertions and reporting constructs may be ignored by synthesis. Treat the synthesizer report, not language legality alone, as the final answer about implementability.

Names should reveal direction and role:

Suffix/prefix Meaning Example
_i Input port button_i
_o Output port led_o
_io Bidirectional port data_io
_n Active-low signal reset_n_i
r_ or _q Registered/current value count_q
next_ or _d Next value next_state
C_ Constant C_CLOCK_HZ
G_ Generic G_WIDTH

Consistency matters more than the exact convention.

Where to continue