Sources and further study

Prefer primary documentation for device behavior and tool commands. This library explains and connects the concepts; the current vendor manuals remain the authority for version-specific details.

Basys 3

• Digilent Basys 3 reference manual (PDF) — board architecture, 100 MHz clock, buttons, displays, USB-JTAG/UART, VGA, Pmods, and electrical information.
• Digilent master XDC repository — official constraint templates.
• Basys 3 master XDC — pin names, package pins, I/O standards, and clock constraint template.

AMD Vivado

• UG900 — Vivado Design Suite User Guide: Logic Simulation — compile, elaborate, and simulate flows; XSim command-line tools.
• UG901 — Vivado Design Suite User Guide: Synthesis — synthesis options, strategies, and inference.
• UG901 — HDL Coding Techniques — coding styles for registers, RAM, arithmetic, and other FPGA structures.
• UG903 — Using Constraints: Timing Constraints — clocks, I/O delays, timing exceptions, and analysis.
• UG903 — Recommended Constraints Sequence — dependency order for constraints.
• UG949 — Clock Domain Crossing — CDC architecture and methodology.

Language

• IEEE 1076 VHDL standard page — formal language standard information.
• Use ieee.std_logic_1164 for multi-valued logic and ieee.numeric_std for portable signed/unsigned arithmetic.

Verification frameworks

• VUnit user guide — Python-based test discovery, configurations, checks, logging, and CI integration.
• VUnit run library — VHDL test-runner API.
• OSVVM documentation — constrained random, functional coverage, scoreboards, alerts, and verification methodology.
• OSVVM libraries — source and package overview.
• OSVVM Scripts — simulator build and regression scripting, including current simulator-status notes.

Version notes for this library

Verified local context when created:

Component	Version/context
Vivado	2026.1, 64-bit
Installation	D:\FPGA\2026.1\Vivado
Target	Basys 3 / xc7a35tcpg236-1
Simulation standard	VHDL-2008
MkDocs	1.6.1
Material theme	9.7.7
Static i18n plugin	1.3.1

Documentation URLs and tool capabilities evolve. For a future Vivado release, verify command options with:

xvhdl.bat -help
xelab.bat -help
xsim.bat -help
vivado.bat -version

Learning rule

When examples disagree:

1. Check target family and board revision.
2. Check VHDL standard.
3. Check Vivado/simulator version.
4. Prefer current vendor and board documentation.
5. Reduce the issue to a minimal self-checking example.